1. Field of the Invention
The present invention relates to a long-channel MOS transistor and, more particularly, to a long-channel MOS transistor that utilizes a schottky diode to increase the threshold voltage of the transistor.
2. Description of the Related Art
An n-channel metal-oxide-semiconductor (MOS) transistor is a four-terminal device which controls the current that flows between two of the terminals by modulating the voltage which is applied to the third or fourth terminal.
FIG. 1 shows a cross-sectional diagram of a conventional n-channel MOS transistor 100. As shown in FIG. 1, transistor 100 includes spaced-apart n+ source and drain regions 112 and 114 which are formed in a p-type substrate 110, and a channel region 116 which is defined between source and drain regions 112 and 114. Source and drain regions 112 and 114, in turn, represent the first two terminals of the device while substrate 110 represents the third terminal.
In addition, transistor 100 also includes a layer of gate oxide 120 which is formed over channel region 116, and a gate 122 which is formed over gate oxide layer 120. Gate 122 represents the fourth terminal of the device.
In operation, electrons flow from source region 112 to drain region 114 when an electric field is established between source and drain regions 112 and 114, the drain-to-substrate junction is reverse biased, and a gate voltage equal to or greater than the threshold voltage of transistor 100 is applied to gate 122. These conditions can be met, for example, when ground is applied to substrate 110 and source region 112, and one volt is applied to drain region 114.
The gate voltage applied to gate 122 attracts electrons to the surface of substrate 110 in channel region 116. When a minimum number of electrons has been attracted to the surface of substrate 110 in channel region 116, the electrons form a channel which allows the electrons in source region 112 to flow to drain region 114 under the influence of the electric field. The threshold voltage defines the minimum gate voltage that must be applied to gate 122 to attract the minimum number of electrons to the surface of substrate 110 to form the channel.
The threshold voltage of transistor 100 is adjusted by implanting the surface of substrate 110 in channel region 116 with an p-type dopant which, in turn, decreases the number of available electrons at the surface of substrate 110. Since fewer electrons are available, a higher gate voltage is needed to attract the minimum number of electrons that are required to form the channel.
MOS transistors are formed in a photolithograhpic process with a design rule that corresponds to the particular process being used. The design rule specifies, among other things, the minimum length of the channel region. To minimize the silicon area consumed by a MOS circuit, the circuit is largely implemented with transistors that have the minimum channel length.
Since the circuit is largely implemented with transistors that have the minimum channel length, the fabrication step that implants dopants into the surface of the substrate in the channel region is commonly optimized to adjust the threshold voltages of the transistors which have the minimum channel length.
One problem with this practice, however, is that circuits often require transistors which have channel lengths that are longer than the minimum. For those transistors with a longer channel length, a lower threshold voltage is realized when the threshold voltage is optimized for a shorter-channel transistor.
FIG. 2 shows a graph that illustrates threshold voltages versus channel lengths. As shown in FIG. 2, when the threshold voltage is optimized for a channel length x, the threshold voltage of a transistor decreases as the channel length of the transistor increases.
The reduced threshold voltages of the longer channel devices lead to increased leakage currents which, in turn, are particularly undesirable in circuits which are utilized in battery-operated devices.
One approach to this problem is to utilize multiple implant steps. In the first step, dopants are implanted into the surface of the substrate to adjust the threshold voltages of the short channel transistors while the long channel transistors are protected from the implant.
In the second step, dopants are implanted into the surface of the substrate to adjust the threshold voltages of the long-channel transistors while the short-channel transistors are protected from the implant. By utilizing two implant steps, the dopant concentration for the short and long channel lengths can be separately optimized.
The drawback to this approach, however, is that utilizing separate implant steps requires separate masks which, in turn, increases the cost of fabricating the circuit. Thus, there is a need for a long-channel MOS transistor which has a higher threshold voltage when the transistor is fabricated with a single threshold-voltage implant step that is optimized to set the threshold voltage of a short-channel transistor.